In the production of microelectronic devices, integrated circuits utilize multilevel wiring structures for interconnecting regions within devices and for interconnecting one or more devices within integrated circuits. Conventionally, forming interconnect structures begins with forming a lower level of wiring followed by the deposition of an interlevel dielectric layer and then a second level of wiring, where the first and second wiring levels may be connected by one or more metal filled vias.
Interlevel and/or intralevel dielectrics (ILDs), such as silicon dioxide (SiO2), are used to electrically isolate active elements and different interconnect signal paths from each other. The electrical connections between different interconnect levels are made through vias that are formed in the ILD layers. Typically, the vias are filled with a metal, such as copper, aluminum or tungsten.
Recently, there has been great interest to replace SiO2 with low dielectric constant (“low k”) materials as the intralevel and/or interlevel dielectrics in interconnect structures. By “low k’ it is meant a dielectric material (organic or inorganic) having a dielectric constant that is less than silicon dioxide (e.g., k of less than about 4.0, as measured in a vacuum). Examples of low k materials include: organic dielectrics containing atoms of C, O and H such as thermosetting polyarylene ethers; and inorganic dielectrics containing atoms of Si, O and H, with C being optional. Examples of the latter include carbon doped oxides (also referred to as “SiCOH”), silsesquioxanes, organosilanes and other like Si-containing materials.
It is desirable to employ low k materials as insulators in interconnect structures because low k materials reduce the interconnect capacitance. Accordingly, low k materials increase the signal propagation speed, while reducing cross-talk noise and power dissipation in the interconnect structure.
The main problem with low k materials is that they lack mechanical rigidity and easily crack when subjected to thermal and mechanical stresses. That is, prior art low k dielectrics exhibit high crack velocity (on the order of about 1E-10 m/sec or greater at a film thickness of 1.2 μm) and stress (on the order of about 60 MPa or greater), while exhibiting low modulus (on the order of about 7.5 GPa or less) and hardness (on the order of about 1 GPa or less). These mechanical properties become poorer as the dielectric constant of the material is decreased. For instance, the crack velocity, stress, modulus and hardness of a porous low k material are worse than its corresponding nonporous low k material.
Poor mechanical properties of low k dielectrics may lead to device failure or degradation over extended periods of time. For example, dielectric films that have a high crack velocity have a high tendency to form cracks within said film during further processing and use, which greatly reduces the reliability of the semiconductor device that includes such films.
Improved mechanical properties of low k dielectrics have been achieved in the prior art by treating the films post deposition. For example, curing or treatment using thermal, UV light, electron beam irradiation, chemical energy or a combination of these has been used to stabilize the low k dielectric material and to improve the mechanical properties of the same. While such post deposition treatments are possible, they add extra processing steps and thus cost to the manufacturing of the dielectric film.
The above problem with crack formation is not only limited to low k dielectrics, but instead it applies to other materials which become fragile when they are subjected to thermal and mechanical stresses.
In view of the above, there is a need for providing a dielectric stack wherein the mechanical properties such as crack velocity, stress, modulus and hardness are improved without the need of subjecting the dielectric stack to any post deposition treatments.